1. Field
The present innovations relate to relate to provision, control and/or other aspects of clock signal operation(s).
2. Description of Related Information
Numerous computer and chip applications entail provision of a secondary clock signal that is synchronized to a reference clock. Many systems and techniques associated with Delay-Locked Loop (“DLL”) circuits, for example, include clock generators used to synchronize the output clocks with the input reference clock(s) for high-speed applications, such as with synchronous SRAM and DRAM. In general, high-speed digital systems often utilize clock generators with improved tuning or other features to improve performance.
As set forth below, one or more exemplary aspects of the present inventions may overcome such shortcomings and/or otherwise impart innovative aspects by, for example, providing circuitry with improved ability to maintain a locked state of a clock signal despite jitter or noise.